Boundary Scan JTAG Includes:
What is Boundary Scan / JTAG Boundary scan description language, BSDL Design for test with boundary scan JTAG Spec & IEEE 1149 Standard JTAG TAP & connector IEEE 1149.6 (AC coupled JTAG) Compact JTAG cJTAG IEEE 1149.7 IJTAG, IEEE 1687
IEEE 1687 is a proposed IEEE Standard for the access and operation of embedded instruments. It is also referred to by the name IJTAG or Internal JTAG.
The new IJTAG standard will enable a far greater degree of internal test to be accomplished, and with the level of intellectual property, IP being incorporated into ASICs and FPGAs, etc, this is a growing issue.
As boundary scan, defined under IEEE 1149.1 became better established, the capabilities of the JTAG test access port, TAP, interface were explored. The interface allowed for a much greater level of access into the core of circuits and chips themselves without the need for intrusive access.
The development of IJTAG has come about to a large degree because of the growing level of functionality within each silicon chip or die. These days, manufacturers do not just use their own IP on the chip, but also that bought in from other specialists.
Even though the different functional modules within the overall die have their operation and interfaces specified, there is still a great need for integration testing, even if many simulations have been performed. This testing is not always easy to achieve because access to a die is obviously difficult.
To overcome this issue, on board test instruments can be incorporated into the system and the boundary scan JTAG interface used to access them and control them.
To ensure the greatest level of functionality the new IJTAG system defined by IEEE 1687 provides additional access and functionality over that which could be obtained from the basic JTAG TAP.
IJTAG uses the JTAG TAP as the primary interface, but extends the operation considerably. One of the key features is that it standardises the interface for embedded instruments, along with the description of their operation, and connectivity through the design hierarchy.
IJTAG is simple to implement and use because of the plug-and-play approach for both in-house and third party elements.
The key advantages and elements of the IJTAG system are summarised in the table below:
|External interface to internal elements.||Instrumentation control is vendor specific.||Standardised and with plug-and-play capability.|
|Internal control.||Ad-hoc and typically vendor specific.||Standard protocol.|
|Instrument access.||manually defined at the JTAG TAP interface.||Automated re-targeting from IJTAG TAP to instrument through a logical hierarchical structure.|
|Register size||Fixed for each instruction.||Variable.|
Two elements of the IJTAG interface that are key to its operation.
- Instrument Connectivity Language, ICL: The Instrument Connectivity Language is based on the design description. It focuses on the information necessary to write to or to read from the instrument, i.e. typically the tests required. In other words the ICL essentially describes where the IJTAG Test Data Registers, TDRs are, the scan paths that connect and access them, how and when these scan paths should vary. It also describes the connections between the IJTAG scan paths and the boundary-scan TAP controller on the device, and the parallel connections between the embedded IJTAG instruments and the IJTAG TDRs.
- Procedural Description Language, PDL: This language defines the syntax of the read, write and scan operations. The PDL defines the operations and functions of the instrument, and it is converted into test vectors that are associated with each IJTAG instrument that is within a device. A further function of the PDL is to document the actions and sequences of the instruments.
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