Digital PLL Frequency Synthesizer

The digital PLL RF frequency synthesizer works by placing a digital frequency divider into PLL between the VCO & phase detector and by changing the division ratio of the divider, the output frequency changes.

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The digital PLL RF frequency synthesizer gains its name from the fact that it uses digital techniques to control the output frequency.

The Digital PLL synthesizer uses a digital divider placed between the VCO and phase detector. As the divider uses digital techniques, it is possible to change the division ratio of the divider and thereby change the output from the phase locked loop synthesizer.

The digital PLL synthesizer is particularly useful because it can be controlled by a set of digital lines and these could come from a microprocessor or controller. In this way considerable degrees of functionality can be added to any system using the digital PLL synthesizer.

Digital synthesizer basics

The way in which a digital divider is added to the frequency synthesizer loop can be seen in the diagram below.

Basic block diagram of indirect PLL digital frequency synthesizer
Basic digital frequency synthesizer

Programmable dividers or counters are used in many areas of electronics, including many radio frequency applications. They take in a pulse train like that below, and give out a slower train. In a divide by two circuit only one pulse is given out for every two that are fed in and so forth. Some are fixed, having only one division ratio. Others are programmable and digital or logic information can be fed into them to set the division ratio.

Operation of a digital divider in a digital frequency synthesizer
Operation of a digital divider
In this case the division ratio is 3

When the divider is added into the circuit the phase locked loop, PLL, still tries to reduce the phase difference between the two signals entering the phase comparator. Again when the circuit is in lock both signals entering the comparator are exactly the same in frequency. For this to be true the voltage controlled oscillator must be running at a frequency equal to the phase comparison frequency times the division ratio.

It can be seen that if the division ratio is altered by one, then the voltage controlled oscillator will have to change to the next multiple of the reference frequency. This means that the step frequency of the synthesizer is equal to the frequency entering the comparator.

Frequency step increments

It can be seen from the operation of the basic digital frequency synthesizer, that the output frequency is 'n' times the phase comparison frequency, where 'n' is the division ration. Changing the division ratio by one is the smallest frequency change that can be made.

As a result it can be seen that the smallest frequency change that can be made is equal to the comparison frequency, i.e. the phase detector frequency. In the basic format for the digital frequency synthesizer, this is equal to the reference frequency.

Most synthesizers need to be able to step in much smaller increments if they are to be of any use. Often step sizes of 10 kHz or 25 kHz are required where a radio operates within different set channels, and for radios that require continuous tuning, then step sizes of 100 Hz or less may be required.

To achieve this the comparison frequency must be reduced. This is usually accomplished by running the reference oscillator at a frequency of a MegaHertz or so, and then dividing this signal down to the required frequency using a fixed divider. In this way a low comparison frequency can be achieved.

The reference oscillators typically run at frequencies of a few MHz, often 5 MHz or 10 MHz because at these frequencies the performance is better and the size of the crystal is achievable.

Indirect PLL digital frequency synthesizer with division of reference signal to provide smaller step sizes
Indirect digital frequency synthesizer with reference signal divided to provide smaller step sizes

Using a frequency divider after the reference generator enables the low phase comparison frequency while allowing the reference oscillator to run at a convenient frequency, often around 10 MHz.

When developing a digital synthesizer with a low reference frequency, it means that the programmable divider has a much higher division ratio as it needs to divide down from the output frequency to the lower comparison frequency. This can lead to issues with delays through the divider as well as high phase noise and the like.

The block diagrams above show the basic formats for digital frequency synthesizers. In many real applications, the RF synthesizer circuit may be more complications, sometimes consisting of multiple loops to enable the required levels of performance to be achieved..

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