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Fractional N frequency synthesizers provide a convenient solution to the issue of small step sizes without requiring a huge division ratio.
This overcomes a number of performance issues associated with the very high division ratios in the digital divider of the phase locked loop that can lead to a number of performance issues.
Using traditional techniques the output frequency is an integral number multiplication of the phase detector comparison frequency, this means that changing the division ratio by one, changes the frequency by an amount equal to the comparison frequency. For very small step sizes this means that the comparison frequency must be small and the division ratio large.
As this leads to several performance issues, it means that fractional N synthesis is a very attractive option.
Requirement for fractional n synthesis
A fractional n synthesizer uses the basic digital PLL loop. It has a VCO, phase detector, loop filter, divider and could even utilise a mixer within the loop as well.However to explain its operation, the case will be used of a simple digital loop with a divider only added to the basic PLL.
Using this loop the phase detector will compare the two signals entering, i.e. the reference and the divided VCO signal. The loop will lock when the two signals entering the detector are of the same frequency. This means that the VCO will be operating at a frequency equal to the division ratio times the phase comparison frequency.
To achieve small steps between channels of frequencies, while still offering a reasonable operating frequency requires a very high division ratio. For example a loop operating at 10 MHz and requiring a 100 Hz step size will need a division ratio of 100 000. This perfectly feasible, but it does impact the loop performance. As the loop bandwidth must typically be around a tenth of the reference comparison frequency, this would mean, for the above example figures a loop bandwidth of only 10 Hz. This results in loss of performance:
- Slow PLL frequency switching time
- Large passive component sizes
- High phase noise at frequencies close to the carrier, i.e. within loop bandwidth and VCO phase noise not reduced further out
Another option is to use a multiple loop synthesiser, but this has significant cost implications.
A much cheaper option, while still retaining a general high level of performance is to use a fractional n frequency synthesizer.
Fractional n synthesis concept
The concept behind fractional n synthesis, is very much as the name indicates: the divider takes on a fractional division ratio rather than an integer one that would be normally expected. To achieve this, the divider alternatives between division ratios. Typically it will change between N and N+1 - the proportion of the various division ratios determined to give the required frequency. The division ratio range of N and N+1 gives frequencies between the two division ratios. Also switched modulus counters giving counts between N and N+1 are available.
The advantage of using fractional n synthesis is that the step frequency can be small while still allowing a high comparison frequency and loop bandwidth to improve the overall synthesizer performance.
When using a dual modulus divider it is easy to calculate the overall effective division ratio. To determine the effective division ratio, it is necessary to know the two division ratios and the number of VCO cycles for which each division ratio is effective. Therefore the effective division ratio can be calculated from the formula:
Neff = overall division ratio
A = number of cycles divided by N
B = number of VCO cycles divided by N+1
Fractional N synthesis spurious emissions
It can be imagined that the change in division ratio over the period of the VCO cycles causes some disruption to the system. This results in close in spurious emissions that appear on the output of the factional N synthesiser.
The periodic modulus changes causes a phase error accumulation which accumulates over N reference cycles of the divider. This phase error translates into periodic disturbances in the VCO control voltage and in turn this results in the generation of spurious signals that are relatively close in to the wanted carrier.
This phase accumulation occurs because the average of the feedback frequency is equal to the reference frequency. As a result, the phase error will accumulate over N reference cycles before being reset.
There are a number of ways of reducing the effects of these spurious signals. The accumulating phase error can be cancelled out - a method that was patented by Racal in a scheme they referred to as Digiphase. Alternatively the modulus switching can be accomplished randomly so that the sidebands are masked as noise. This reduces the distinct sideband levels in favour of a higher overall sideband noise level.
Fractional N synthesis provides a very convenient way of providing small step sizes whilst still retaining a high comparison frequency. This significantly improves the performance in terms of the phase noise caused by the multiplication of the phase detector and reference that occurs within the loop bandwidth whilst also improving the settling time and also loop stability. The major downside of fractional N frequency synthesis results from spurious signals that are generated by the system. Fortunately these can be minimised to the extent that they are not a problem. Accordingly fractional N frequency synthesis is a technique that can be used to good advantage.
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