SDRAM Memory Chip Architecture

Understanding SDRAM chip architecture helps to clarify some of the operation of SDRAM technology. There are differences between implementations by different manufacturers, but many areas of commonality.

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When using SDRAM it often helps to have a basic understanding of the SDRAM chip architecture. This gives some additional insights into the way the SDRAM chip operates.

SDRAM architecture also greatly impacts the design of the integrated circuit itself. Aspects such as the physical positioning of areas for the memory cells themselves as well as that for the control circuitry are of great importance.

Basic SDRAM architecture

The SDRAM chip architecture is organised with the memory cells organised into a two dimensional array of rows and columns.

To address a particular memory cell within the overall SDRAM, it is necessary first to address the required row, and then the specific column. This selects the column within the row. This isolates the data storage elements to be read from or written to.

An SDRAM row is called a page. Once the row is open it is possible to address multiple columns addresses on the row. Using this technique improves the memory access speed, reducing latency because the row address does not have to be re-sent and set-up. Each time the row is opened it naturally takes time.

As a result, the row address is taken as the higher order address bit elements and the column as the lower ones.

The row and column elements are sent separately for a variety of reasons including the successive addressing of column elements once a row is open. As a result, the row and column addresses are multiplexed onto the same lines - this significantly reduces the package pin count, and this has a major impact on the overall chip cost as one major element of the chip cost is its package.

It should be noted, though, that the row address size is normally larger than the column address because the power of the chip is not related to the number of columns, but the number of rows does impact this figure.

SDRAM chip architecture

The circuit architecture of the SDRAM chip is one aspect of the SDRAM architecture. There are also the chip architecture aspects.

The actual chip SDRAM chip architecture will vary according to the manufacturer, and it will also depend to some extent on the size of the SDRAM.

The SDRAM architecture can be split into two main areas:

  • Array:   This element of the SDRAM architecture is the area of the chip where the memory cells are implemented. It is normally divided into a number of banks, which in turn is split into smaller areas which are termed segments.
  • Periphery:   This is the area of the chip where control and addressing circuitry is located as well as items such as line drivers and sense amplifiers. The chip periphery often separates the array banks and segments from each other.

Looking at the relative areas occupied by the array and the periphery it is possible to determine a figure of merit for the proportion of the overall area occupied by the actual memory. This is often termed the array or cell efficiency because the aim of the chip is to provide memory - the periphery, although important does not increase the size of memory.

The array or cell efficiency for the chip is normally expressed as a percentage:

Array / cell efficiency (%) = Array area Overall chip area 100

As the periphery does not contribute to the actual amount of memory on board, companies endeavour to increase the array efficiency. Figures are typically in the region of 60 - 70%.

Although the actual SDRAM chip architecture varies from one manufacturer to the next there are several common aspects to the architecture design. Knowing how the SDRAM chip is organised, helps understand its operation a little more.

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