DDR4 was the fourth generation of double data rate SDRAM and it provided a significant increase in performance.

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DDR4 SDRAM was the fourth generation of SDRAM which introduced a number of further developments to enable higher speed operation.

DDR4 SDRAM was developed as a result of the growing industry need for higher performance memory and in this case SDRAM. It was first introduced around the latter half of 2016.

DDR4 SDRAM basics

DDR4 SDRAM provided a significant improvement in performance over the previous DDR3 chips. A summary of some of the highlights of DDR4 SDRAM are listed below:

  • Data rates:   At the time DDR4 was introduced, it was anticipated that DDR3 would peak at a data rate of 1.6 Giga transfers per second per pin. Accordingly this was set as the entry point for DDR4 SDRAM. This transfer rate is expected to rise to twice this level, i.e. 3.2 Giga transfers per second, with possible increases on this.
  • Internal databanks:   Internal banks are increased to 16 (4 bank select bits), and with up to 8 ranks per DIMM.
  • Operating voltage:   DDR4 chips use a 1.2 V supply with a 2.5 V auxiliary supply for wordline boost called VPP. This is compared to the standard 1.5 V of DDR3 chips, with lower voltage variants at 1.05 V that became available after the first introduction.
  • DQ bus:   . One of the other performance features planned for inclusion in the DDR4 SDRAM standard are a pseudo open drain interface on the DQ bus.
  • Data width:   DDR4 SDRAM offers three values of data width: x4, x8 and x16.
  • Prefetch:   DDR4 SDRAM architecture uses 8n prefetch with bank groups. This includes two or four selectable bank groups. This enables the DDR4 SDRAM to have separate activation, read, write or refresh operations underway in each of the unique bank groups. This techniques increases the memory bandwidth and efficiency. It is particularly suited for memory applications where small levels of granularity are required.
  • Differential signalling:   For DDR4 SDRAM the clock and strobe lines utilise differential signalling.
  • Protocol updates:   A variety of protocol changes were introduced on DDR4 memories:
    • Parity on the command/address bus
    • CRC on the data bus
    • Independent programming of individual DRAMs on a DIMM, to allow better control of on-die termination.
    • Data bus inversion

The DDR4 specification defined standards for ×4, ×8 and ×16 memory devices with capacities of 2, 4, 8 and 16 Gib.

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